Aspects are related generally to computer-based communication systems, and more specifically to a cut-through buffer crossing domains with variable frequencies in a computer system.
Peripheral component interconnect express (PCIe) is a component level interconnect standard that defines a bi-directional communication protocol for transactions between input/output (I/O) adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus.
Packets can be received and processed in different clock domains asynchronously. Managing an asynchronous boundary crossing through a buffer, where source and destination clock domains are variable, typically has a high degree of latency and complex handling logic. For example, data can be read faster than it is written, resulting in a potential underrun/read ahead condition. There must be guarantees that the read side will never underrun regardless of the read and write clock relationships. In some system designs, packets must be transmitted continuously once they are started with no pacing logic allowed. Thus, there is a need to reduce complexity and latency in asynchronous boundary crossings with variable frequencies in a computer system.